1. Field of the Invention
The present invention relates to testing of integrated circuits, and more specifically to a method and apparatus for testing of modules operating with different characteristics of control signals using scan based techniques.
2. Related Art
Scan based techniques are often employed to test integrated circuits (ICs). In a typical scenario, memory elements (e.g., flip-flops) contained in an IC are connected in sequence, and a desired sequence of bits (“test pattern”) is scanned into the memory elements in corresponding clock cycles. Automatic Test Pattern Generation (ATPG) techniques, wherein the test patterns for complex designs are generated automatically, often use such scan based techniques.
The combinatorial logic elements contained in the IC are then evaluated based on the scanned test pattern. The results thus generated may be stored in the corresponding memory elements. The generated outputs may be examined (potentially by scanning/shifting out the bits stored by the memory elements) to verify whether the IC operates in a desired manner.
Control signals are often used to control and coordinate the activities of various elements contained in an IC. For example, one logic level of a signal (“scan enable signal”) may cause a test pattern (or results) to be shifted into (out of) memory elements (“shift mode”), and another logic level of the signal may then cause the evaluation/capture of outputs of the combinatorial logic (“capture mode”).
Another example of a control signal is a clock signal, which controls the specific time instances at which the bits are scanned and evaluated. In general, the transitions are controlled by the occurrence of an edge (rising or falling) or upon a specific active state (logic high or logic low), as is well known in the relevant arts. For example, the scan enable signal transitions may be controlled on clock signal edges or clock signal levels. Merely for illustration, the description in the present application is provided assuming the transitions occur on edges.
ICs often contain modules, which generally refer to distinct units, typically provided for a specific purpose. For example, a module may operate as a random access memory, and another module may be implemented to process analog signals according to desired digital signal processing (DSP) techniques.
Different modules may be designed to operate with different characteristics of control signals during scan based tests. For example, one module may be designed to transition from one state to another on a rising edge of a clock signal and another module may be designed to transition on a falling edge of the clock signal. Similarly, one module may require change in levels of scan enable (SE) signal to be synchronous with a rising edge and another module may require change in levels of SE signal to be synchronous with a falling edge of the clock signal.
Such differences in operation of modules can be due to various reasons. For example, a designer of a system on a chip (SOC) may use modules (often referred to as “intellectual property cores”, IP cores) provided by third parties, who may design their respective modules to operate with different characteristics of control signals during testing using scan based techniques.
It is often desirable that integrated circuits be tested using scan based techniques even in situations when different modules operate with different characteristics of control signals. In particular, in a SOC type scenario in which different IP cores may be provided by different designers with potentially different characteristics of the control signals, it is desirable that the SOC be tested comprehensively.
In one prior approach, each module is tested in isolation by providing corresponding control signals with different characteristics. Since each module is tested in isolation, control signals may be generated with corresponding characteristics. Accordingly, all modules of an integrated circuit may be tested at least to some extent, even if the modules operate with different characteristics.
Several disadvantages may be presented due to such a prior approach. For example, the cross module operation (i.e., output generated by one module being used by another module) may not be tested in such an approach. As a result, the approach may also not be able to test the interconnect paths between the modules at the speed at which the paths are likely to be operated in an application use scenario.
Additional challenges may be presented to designers using of ICs modules from potentially different vendors (i.e., IP cores being available from different vendors). Typically, a designer of an IP core designs the corresponding circuit ahead of the time an SOC designer designs the SOC, hence the IP core designer may not know the specific characteristics of the control signals with which the multiple IP cores in an SOC would operate. As a result, the SOC designer cannot influence/change the characteristics of the control signals required for testing individual IP cores.
An SOC designer may attempt to design the test related circuits consistent with the design of an IP core. Unfortunately, different IP cores may present conflicting requirements with respect to the characteristics of the control signals and different portions provided by the SOC designer may need to inter-operate with several such IP cores. As a result, cross module testing may again pose challenges.
At least for components such as SOCs to be tested as comprehensively as possible, an approach is needed which allows testing of modules operating with different characteristics of control signals using scan based techniques (at least for reasons noted above).
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.